It is presently known to package a processor with an image sensor device in a stacked System-In-Package (SIP) configuration. See for example U.S. Pat. No. 6,521,881, which is incorporated herein by reference. In such a configuration, the processor is specifically designed to process signals produced by the image sensor die. The image sensor die is connected to the processor via wirebonding and an interposer. One drawback with this configuration is that the sensor output signals have a relatively long travel path (i.e. through wirebonding, through interposer, and through more wirebonding), which reduces efficiency and limits the capability of the image sensor system. The sensor die has basic pre-processing functions, such as converting analog signals to digital signals. However, the sensor die does not have any post processing capability. Also, this configuration consumes an excessive amount of space, both vertically and horizontally.
One conventional solution is to form the processor and the image sensor in a 2D System-On-Chip (SOC) configuration. See for example European Patent 1686789. In this configuration, the processor is formed on the same die as the image sensor. This design improves (reduces) the signal travel distance compared to the SIP configuration, but the travel distance is still relatively long. Also, by using a SOC configuration, the processer area can be significantly limited, thus limiting the number of available transistors forming the processor (and therefore limiting its processing capabilities and performance). In some cases, only the basic image sensor control logic is integrated on the same die as the sensor.
Another conventional solution is 2.5D/3D packaging techniques, which involve mounting separately fabricated and completed semiconductor modules/wafers on top of one another. This solution reduces overall size (somewhat), and can reduce travel signal distance (somewhat). However, this solution still requires careful integration of separately fabricated components, and only reduces size and travel signal distance only to a certain extent.
Many conventional mobile devices rely on the mobile device's main processor (i.e. the application processor) to process image sensor signals. The steps of image capturing and signal processing include the CMOS image sensor capturing light information and generating analog signals, converting the analog information to raw digital data, and transferring the raw digital data to the application processor. The application processor uses image processing software to turn the raw digital data into a digital image. This process flow relies on the application processor for digital image processing. However, digital image processing requires a lot of processing power and computation capability from the processor, and many advanced computational algorithms are not well suitable for the mobile phone platform due to such constraints. While the application processor can have great flexibility, the tradeoff however is application specific processing, meaning the processor can process the data but not in a fast and efficient manner. The application processor is also relatively far from the image sensor, so any feedback or adjustments to the sensor device are greatly delayed. The application processor needs to manage not only the image sensor, but the whole mobile device while processing the raw image data. Raw image data is very large in size, and transferring such files costs substantial resources and huge delays.
Some mobile devices use a 3D-SOC chip, which is separate from the application processor chip, to process image data. The image capturing process, performed by the 3D-SOC chip, includes capturing light information and generating analog signals, converting analog information to raw digital data, processing the raw digital data and converting it into digital images with the help of hardware acceleration, and transferring the processed digital image to the application processor. This process flow enables advanced computational algorithms that are not well suited for the mobile phone platform. The 3D-SOC processor is application specific to digital image processing. The hardware acceleration allows the raw data to be processed in a fast and efficient manner. The 3D-SOC chip has an integrated processor that can be less than 2 μm under the image sensor, such that signal latency is greatly reduced. The configuration enables speedy and advanced camera system self-correction mechanism based on the raw digital data, and produces the best possible set of raw digital data for digital image processing. The application processor is freed to manage other tasks, improving overall mobile device performance. Processed image data is very small in size, so transferring such file data in the current mobile device is negligible on the system task load. Therefore, an improved 3D-SOC camera chip which is smaller, more reliably fabricated, and provides shorter signal travel distances, is needed.